NPTEL Computer Architecture Assignment 4 Answers 2022

NPTEL Computer Architecture Assignment 4

Are you looking for the Answers to NPTEL Computer Architecture Assignment 4? This article will help you with the answer to the National Programme on Technology Enhanced Learning (NPTEL) Course “NPTEL Computer Architecture Assignment 4″

What is Computer Architecture?

This is an introductory computer Architecturecourse for beginners. We will start out with a discussion on binary representations, and a discussion on number systems (1’s complement and 2’s complement). Then, the course will move on to discuss assembly languages and computer arithmetic. Once, we are done with the fundamentals, we shall look at the design of a simple processor, concepts of pipelining, and the design of a modern memory system.


Average assignment score = 25% of the average of best 8 assignments out of the total 12 assignments given in the course.
Exam score = 75% of the proctored certification exam score out of 100

Final score = Average assignment score + Exam score

YOU WILL BE ELIGIBLE FOR A CERTIFICATE ONLY IF THE AVERAGE ASSIGNMENT SCORE >=10/25 AND EXAM SCORE >= 30/75. If one of the 2 criteria is not met, you will not get the certificate even if the Final score >= 40/100.

Below you can find the answers for the NPTEL Computer Architecture Assignment 4

Assignment No.Answers
Computer Architecture Assignment 1 Click Here
Computer Architecture Assignment 2 Click Here
Computer Architecture Assignment 3 Click Here
Computer Architecture Assignment 4 Click Here

NPTEL Computer Architecture Assignment 4 Answers:-

Q1.In an ARM machine, the instruction str r1, [r2, #2] corresponds to the ____ addressing mode.

Answer:- d

Q2. Which of the following is not an unconditional branch instruction in the ARM ISA?

Answer:- d

Q3. Which statement is correct regarding the stmfd and ldmfd instructions of the ARM ISA?

Answer:- a

Q4. In an ARM ISA, we have ___ bits for encoding a shifter operand.

Answer:- a

???? Next Week Answers: Assignment 05 ????

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Q5. In the ARM ISA, which of the following instructions corresponds to the pre-indexed addressing mode?

Answer:- b

Q6. In the 16-bit x86 ISA, the _______ register saves the value of the stack pointer at the beginning of a function.

Answer:- c

Q7. In x86, the starting address of the code segment is maintained in the ___ register.

Answer:- d

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Q8. In a _______ memory model, the address specified in the instruction is directly sent to the memory system.

Answer:- a

Q9. In the x86 ISA, the memory operand “[edx * 2]” corresponds to the ____ addressing mode.

Answer:- b

Q10. Which of the following statements is incorrect for x86 assembly?

Answer:- c

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